In modern integrated circuit technologies, numerous device fabrication methodologies have been provided in order to construct insulated-gate field-effect transistors (IGFETs). IGFET devices have important applications in advanced very-large-scale integration (VLSI) or ultra-large-scale integration (ULSI) circuit environments. In fabricating IGFETs, it has heretofore been recognized as desirable to ensure that the source/drain junction regions of the IGFET are shallow and have low parasitic electrical resistance. In sub-micron transistors where the device channel or gate length is scaled down, it is likewise desirable to properly reduce other lateral and vertical dimensions associated with the transistor. In particular, the source/drain junction depth of the transistor should be reduced. Reduced device dimensions and other scaled physical parameters of the device such as doping profiles must be properly controlled or else undesirable effects may occur in operation of the transistor, resulting in transistor performance degradations.
At least two device performance degradation problems are associated with deep source/drain junction regions in scaled IGFET devices. The first problem is the possibility of a device drain current leakage caused by a phenomenon known as drain-induced barrier lowering (DIBL). DIBL causes increased off-state electrical current leakage through the transistor channel. Theoretically and ideally, no subthreshold drain current should pass through a transistor channel for gate-to-source voltages below the nominal transistor threshold voltage. However, as drain-to-source voltage is increased for a constant gate-to-source voltage below the threshold voltage of the device, DIBL causes the drain current of the device to likewise increase due to a lowering of the effective channel potential barrier. Thus, deeper source/drain junction regions cause DIBL which in turn creates a transistor response which departs from ideal device characteristics. This phenomenon is also known as DIBL-enhanced subthreshold leakage.
A second problem associated with deep source/drain junction regions and also closely associated with subthreshold leakage is the occurrence of punch-through leakage and breakdown underneath the transistor channel. Punch-through leakage occurs where a transistor, although in an off-state condition (gate-to-source voltage below the threshold voltage), leaks from a bulk leakage path produced by the connection or proximity of the depletion regions surrounding the individual doped source/drain junction regions of the transistor. Once this leakage current occurs, the transistor gate is no longer fully controlling the conductivity of the device channel. As a result, the transistor, and any circuit implementing it, may become inoperable or work in a fashion other than that which is desired.
An additional concern in the construction of VLSI and ULSI transistor circuits has been the necessary control and effects of refractory metal and metal silicide contacts to various terminals of individual transistors. Refractory metal or metal silicide contacts to the surfaces of transistor gate and source/drain junction regions are achieved based on a self-aligned technique which is well-known in the art. A trade-off, however, exists in selecting the thickness of the refractory metal or silicide contacts. This trade-off results from two opposing considerations. First, a thick metal silicide contact layer is desirable in order to minimize the effective sheet resistance associated with the transistor source/drain junction and gate regions. For submicron technologies, this consideration is particularly important due to the reduced size and the increased speed expectations of the transistor. Second, a thin refractory metal silicide layer is desired in order to minimize source/drain silicon consumption which occurs due to the reduction of the semiconductor source/drain surface by the thermal silicidation reaction of the refractory metal therewith. This requirement will ensure low junction leakage in source/drain junction regions. Thus, these two opposing considerations must be optimized in constructing a transistor which utilizes refractory metal silicide contacts.
Advanced IGFETs employed in metal-oxide-semiconductor (MOS) technologies usually use a stacked gate structure consisting of a lower layer of doped polycrystalline silicon (or known as polysilicon) and a top layer of refractory metal silicide to lower the overall transistor gate parasitic resistance and gate interconnection delay time. The lower layer of polysilicon is usually doped with arsenic, phosphorus, or boron using furnace doping or ion implantation. It is critical that the gate polysilicon doping should be high and uniform, particularly near the gate electrode/gate dielectric interface. Uniform high doping of a thick polysilicon layer requires a rather high temperature annealing step which can also result in unwanted dopant redistribution in the source/drain junction and channel regions of the transistor. On the other hand, lower temperature annealing steps are favored to maintain shallow source/drain junctions and to prevent dopant (such as threshold voltage adjustment dopant implanted in the channel) redistribution in the device channel; however, lower temperature annealing may result in insufficient dopant redistribution in the gate polysilicon and insufficient doping near the gate electrode/gate dielectric interface. This phenomenon degrades device performance. In addition, excessive thermal anneals not only result in deep source/drain junctions, but may also cause dopant penetration from the gate polysilicon to the device channel region via the gate dielectric. These results degrade process control and device parameter spread by changing the transistor threshold voltage and other characteristics. An improved fabrication method is needed to overcome these trade-offs for high-performance transistor structures.
In an effort to solve problems pertaining to deep source/drain junction regions and the formation of refractory metal silicide contacts, a device known as an elevated source/drain transistor has been heretofore developed. An elevated transistor includes doped source/drain semiconductor regions within the semiconductor substrate (or well) of the device, and elevated doped source/drain semiconductor regions disposed at the surface of the semiconductor substrate and immediately over the doped source/drain junction regions. This elevated source/drain structure reduces the problems associated with deep source/drain junction regions and surface refractory metal silicide connections discussed above. Unfortunately, however, the methodologies heretofore known in the art for constructing elevated source/drain transistors have generated a number of trade-offs. Each of these trade-offs gives rise to manufacturing complexity and limitations in the operability of the device. In particular, thermal annealing processes implemented in the manufacture of the elevated source/drain transistor must be accurately controlled in order to accommodate some of the trade-offs. A failure in controlling these annealing processes may result in an inoperable device or a device with parameters dissimilar to those required or specified for it.
Still another concern in the formation of VLSI and ULSI circuits has been the methods used to interconnect devices which are local to one another. One current method suffers inefficiencies by requiring numerous process steps and wasting excess unreacted materials. An alternative known method is problematic because it utilizes interconnecting materials such as refractory metal nitrides having high electrical resistivity which can reduce the overall circuit speed and limit the distance that the interconnect lines can extend. These methods also rely on complex fabrication techniques which may cause process repeatability problems.
There are often numerous processing steps necessary in order to complete the local interconnect process. A first type of interconnection scheme involves forming refractory metal silicide contacts on the transistor source/drain and gate regions, while discarding, and therefore wasting, any excess material (either reacted with nitrogen or unreacted) which extends beyond the dimensions of the transistor active area. Thereafter, an interlevel dielectric is deposited and metal contact holes are formed therein using standard photolithographic and etching processes. Finally, a metal layer is deposited thereby forming contacts between the top metal layer and the refractory metal silicide regions previously formed. A second type of interconnection scheme involves forming refractory metal silicide contacts on the transistor, and retaining selected portions of metal nitride material which are formed over the field insulating regions during refractory metal silicide formation and which extend beyond the active dimensions of the transistor. These selected portions, usually made of refractory metal nitrides, are used as local interconnects; however, these portions have a high electrical resistivity because they have not reacted with a semiconductor as have the silicide contacts on the transistor gate and source/drain regions. The high electrical resistivity severely limits the practical length and efficiency of this type of local interconnect, particularly in submicron technology.
Therefore, a need has arisen for a method and structure involving the construction and interconnection of a high-performance insulated-gate FET which optimize and accommodate the trade-offs and problems identified above.